The present invention relates generally to a method of forming local oxidation isolation structures in semiconductor and/or integrated circuit devices and, more particularly, relates to a method of forming such isolation structures that reduces stress-related defects and that results in a reduced or negligible bird""s beak.
All integrated circuits (ICs) have electric circuits which include a number of isolated devices, e.g., transistors, interconnected through one or more conducting paths. Thus, to fabricate ICs, the individual devices must be created in a silicon substrate in such a way that they are electrically isolated from one another. Isolation of the individual devices ensures that the state (e.g., on or off) and conductance of the individual devices are independently controlled. Without proper isolation, leakage currents may occur, causing power dissipation, noise margin degradation and/or voltage shifts on dynamic nodes. In CMOS circuits, leakage currents may lead to device latch up, which can damage the integrated circuit. Further, without proper isolation, cross-talk between devices may occur, thereby disturbing the logic state of a gate which is made up of a number of the individual devices.
Integrated circuit designers face other challenges that may conflict with the desire for proper isolation. For example, it is commercially important to make the spacing between individual components or devices as small as possible to enable increases in device density (e.g., number of devices per unit area). Furthermore, there is a strong desire in the art to ensure that the fabrication processes which are used to produce the isolation structures are simple to implement and control while, at the same time, these processes should not adversely impact the characteristics of active areas of the semiconductor die which will form the integrated circuit.
To meet these and other challenges in manufacturing semiconductor devices, Local Oxidation of Silicon (LOCOS) has become a widely used processing step in forming lateral isolation structures between devices (e.g., transistors) on a semiconductor die. Indeed, the LOCOS process has become the xe2x80x9cwork horsexe2x80x9d isolation technology for MOS devices down to about 0.5 xcexcm geometries. LOCOS processes are popular, in part, because they produce a fairly planar surface which is highly desirable for resolving and patterning dense features on a semiconductor die.
FIG. 1 illustrates a semiconductor die 10 at one stage of a conventional LOCOS process. A thin layer of a pad oxide of approximately 10 to 50 nm thickness is formed on the surface of a silicon substrate 12. Next, a thicker layer of silicon nitride 16 is deposited on the pad oxide layer 14. The silicon nitride layer 16 may be approximately 100 to 150 nm thick and may be deposited using conventional chemical vapor deposition (CVD) techniques.
In the resulting structure, the pad oxide layer 14 is used to cushion the transition of stresses between the silicon substrate 12 and the nitride layer 16. Such stresses may occur in the nitride layer 16 due to various effects, including: (1) a mismatch between the thermal co-efficient of expansion of the nitride layer 16 and the silicon substrate 12; and (2) a tendency of the growing field oxide (see below) to lift the edges of the nitride layer 16. Such stresses may cause the nitride layer 16 to crack as the field oxide layer is grown, thus defeating the purpose of the nitride layer 16 as an oxidation barrier.
Stresses may also be transmitted from the nitride layer 16 to the silicon substrate 12. These stresses may produce defects in the silicon crystal. In general, the thicker the pad oxide layer 14, the fewer the defects in both the nitride layer 16 and the silicon substrate 12 during the field oxide layer growth. However, a thick pad oxide layer 14 may render the nitride layer 16 less effective as an oxidation mask by allowing lateral oxidation to take place. Consequently, the thinnest pad oxide layer 14 that effectively relieves stress is generally employed.
After the nitride layer 16 is deposited, it may be patterned, for example by using conventional photolithography techniques wherein in a photoresist layer (not shown) is spun on and exposed though a mask. As shown in FIG. 2, the nitride layer 16 and pad oxide layer 14 may then be etched to expose a top surface of the silicon substrate 12 in a region 18 that will become an isolation structure. In other words, the nitride layer 16 and pad oxide layer 14 are patterned so that after the etch they remain only over what will become the active regions in the silicon substrate 12.
With the region 18 still exposed, the silicon substrate 12 is oxidized to form a field oxide region 20 of desired thickness. The result is shown in FIG. 3 where a field oxide region 20 has been grown over silicon substrate 12. Even though this oxide grows mainly in areas where the silicon nitride layer 16 is absent, the oxide generally grows by diffusion, resulting in both vertical growth in the isolation region and lateral growth under the nitride and pad oxide layers, 16 and 14. This lateral growth of the field oxide results in a so-called bird""s beak, because the shape of the oxide grown under the nitride layer resembles that of a bird""s beak. Because it is the beak-to-beak distance xe2x80x9cbxe2x80x9d (see FIG. 4) over the silicon substrate 12 which will define the active transistor area, the smaller the bird""s beak, the closer devices (e.g., transistors) can be packed onto a given substrate. In other words, bird""s beak encroachment leads to active areas that are narrower than originally patterned. What is desired is as small a bird""s beak as possible.
Because of the bird""s beak phenomenon, conventional LOCOS processes are generally considered most appropriate for technologies having transistor gate widths of approximately 0.5 xcexcm, or greater. That is, it has been recognized in the literature (see, e.g., Stanley Wolf, Silicon Processing for the VLSI Era, Vol. 3, Ch. 6, p. 367) that conventional LOCOS technologies are not suitable for device geometries of less than 0.5 xcexcm. To overcome this barrier, some variations of conventional LOCOS have been proposed which attempt to minimize the bird""s beak effect. For example, techniques such as sidewall masked isolation and poly-buffered LOCOS have been developed to reduce the effect of bird""s beak. In general, however, these techniques typically require additional processing steps, therefore making the processes more complex and more costly. Another drawback of conventional LOCOS is that it is susceptible to xe2x80x9cdefectsxe2x80x9d caused by the high stresses generated in the narrow active areas, underneath the nitride layer, during the field oxidation. These defects can degrade the gate oxide quality and transistor performance. The defect generation gets enhanced as the geometries shrink and the bird""s beak encroachment becomes more significant. What is desired, therefore, is a means of forming an isolation structure in a semiconductor substrate having a reduced bird""s beak that does not have the drawbacks and shortcomings of conventional methods and/or known variations thereof.
The present invention concerns a method of forming an isolation region in a semiconductor wafer or die. The semiconductor die generally includes a semiconductor (preferably silicon) substrate, an oxide layer thereon and a nitride layer on the oxide layer. The nitride layer is patterned to expose an isolation region, then subsequently etched so that a region of the nitride layer adjacent to the isolation region has a nearly vertical sidewall. The etch step may be continued or one or more separate etching steps may be conducted to etch the exposed oxide layer (i.e., in the isolation region) and a region having a sloped sidewall with respect to the nearly vertical sidewall of the nitride layer is formed in the silicon substrate. A field oxide is then grown in the isolation region using a high pressure, dry oxidizing atmosphere and/or environment. The high pressure dry ambient during oxidation results in reduced lateral oxidation.
The sloped sidewall of the silicon substrate in the isolation region effectively moves the face of the exposed silicon away from the edge produced by the patterning and etching of the nitride layer. When compared to a non-sloped sidewall region, the encroaching oxidation starts with a built-in offset from the patterning etch. This leads to a reduction of oxide encroachment and may result in a nearly non-existent bird""s beak. The desirable range of slopes for the sidewall of the silicon substrate in the isolation region is approximately 50xc2x0-80xc2x0 with respect to a horizontal plane defined by an approximately planar surface of the silicon substrate at the base of the isolation region (i.e., approximately 10xc2x0-40xc2x0 with respect to the nitride layer sidewall).
The reduced oxide encroachment, due to the sloped sidewall and the high pressure dry oxidation, results in reduced stresses in the nitride and, hence, prevents the formation of defects in the underlying silicon. The dry ambient during oxidation also prevents KOOI defects (which may typically result from the interaction between the nitride and steam used in conventional oxidation).